1. Field of the Invention
The present invention relates to a semiconductor booster circuit and more particularly to a semiconductor booster circuit, such as a charge pump circuit, which is used in an EEPROM (Electrically Erasable and Programmable Read Only Memory) and a flash memory.
2. Description of the Related Art
In recent years, along with the promotion of a single 5V power supply or the promotion of a single 3V power supply for semiconductor integrated circuits such as EEPROMs and flash memories, the boosting has been performed in the integrated circuit. As a result, semiconductor booster circuits such as a Cockcroft Walton circuit and a charge pump circuit have been employed.
FIG. 18 shows a configuration of a conventional semiconductor booster circuit.
As shown in the figure, N-channel MOS transistors Q20 to Q24 are connected in cascade to configure a booster circuit having n stages. The gate terminals of the transistors Q20 to Q24 are connected to the respective source terminals N20 to N24 to which a clock signal xcfx86A or xcfx86B is input through respective capacitors C20 to C24.
As shown in FIG. 19, the clock signals xcfx86A and xcfx86B are in opposite phase with each other. Each of the clock signals xcfx86A and xcfx86B has a period of 1/f and an amplitude of Vxcfx86. The clock signals xcfx86A and xcfx86B are obtained from a clock signal CK through two NAND circuits ND1 and ND2 and three inverters 1V1 to 1V3, and the amplitude Vxcfx86 thereof is equal to a power supply voltage Vdd. Incidentally, in FIG. 18, reference symbol G designates a ground terminal.
As shown in FIG. 18, in this semiconductor booster circuit, the power supply voltage Vdd is output as an input signal from a source terminal N27 of a transistor Q25, and an output voltage VPOUT is output as an output signal from an output terminal N26.
As described in an article xe2x80x9cAnalysis and Modeling of On-Chip High-voltage Generator Circuits for Use in EEPROM Circuits (IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 24, No. 5, October 1989) for example, the output voltage VPOUT of a sort of the semiconductor booster circuit is expressed by the following expressions:
VPOUT=Vinxe2x88x92Vt+n([Vxcfx86xc2x7[C/(C+Cs)xe2x88x92Vt]xe2x88x92IOUT/f(C+Cs)]xe2x80x83xe2x80x83(1)
Vt=Vt0+K2xc2x7([Vbs+2xcfx86f)xc2xdxe2x88x92(2xcfx86f)xc2xd]xe2x80x83xe2x80x83(2)
where Vin is an input of the booster circuit, V0 is an amplitude voltage of the clock signal, f is a clock frequency, C is a coupling capacitance to the clock signal, Cs is a parasitic capacitance in each of stages in the booster circuit, n is the number of stages of the booster circuit, VPOUT is the output voltage in the final stage of the booster circuit, IOUT is a load current in the output stage, Vto is a threshold voltage when a substrate bias is absent, Vbs is a substrate bias voltage (a potential difference between the source and a substrate or a well), xcfx86f is a Fermi potential, Vt is a threshold voltage of the transistor, and K2 is a substrate bias coefficient.
From the expression (1), it is understood that when the load current IOUT is zero and the relation of C/(C+Cs)=1 is established, the output voltage VPOUT is increased in proportion to both a value of (Vxcfx86xe2x88x92Vt) and the number n of stages of the booster circuit. In the conventional booster circuit shown in FIG. 22, since the amplitude voltage Vxcfx86 of the clock signal is equal to the power supply voltage Vdd, the output voltage VPOUT is increased in proportion to both the value of (Vddxe2x88x92Vt) and the number of stages of the booster circuit.
However, in the conventional booster circuit, there occurs a phenomenon that as the level of the output voltage VPOUT is increased, as shown in the expression (2), the threshold voltage Vt of each of the transistors Q20 to Q24 is increased due to the substrate effect.
Therefore, in the case where the stages of the booster circuit are discretely configured in order to prevent the substrate effect from occurring, the level of the output voltage VPOUT is increased in proportion to the number n of stages of the booster circuit. On the other hand, in the case where the transistors Q20 to Q24 are integrated to be formed on the same substrate, since the substrate effect occurs, as the number n of stages of the booster circuit is increased, the value of (Vddxe2x88x92Vt) is decreased.
As a result, as shown in FIG. 20, along with the increasing of the number of n of stages of the booster circuit, the output voltage VPOUT is decreased to a level lower than a value which is obtained when no substrate effect occurs, and is saturated at the point where the value of (Vddxe2x88x92Vt) becomes zero. This means that no matter how the number n of stages of the booster circuit is increased, there is a limit in the resultant output voltage VPOUT. FIG. 24 shows the relationship between the power supply voltage Vdd and a maximum output voltage when the number n of stages of the booster circuit is made infinitely large. When the number n of stages of the booster circuit is made infinitely large, in the case where no substrate effect occurs, the resultant output voltage VPOUT becomes theoretically infinite. On the other hand, in the case where the substrate effects actually occurs, the resultant output voltage VPOUT is limited to a value depending on the power supply voltage Vdd. That is, in the conventional booster circuit, there arises a problem that in the case where the level of the power supply voltage Vdd is low, the desired output voltage VPOUT can not be obtained even if the number n of stages of the booster circuit is set to any large value.
For example, in the conventional booster circuit shown in FIG. 18, in the case where the power supply voltage Vdd is 2.5V, and the threshold voltage Vto is 0.6V when no substrate effect occurs (the substrate bias voltage is 0V), when the number n of stages of the booster circuit is set to 20, 20V can be obtained as the output voltage VPOUT. However, in the case where the power supply voltage Vdd is 2.0V, even if the number n of stages of the booster circuit is set to 100, only 12V can be obtained as the output voltage VPOUT.
On the other hand, in JP-A-61-254078, there is disclosed a Cockcroft type booster circuit in which a threshold voltage Vt of a MOS transistor in the subsequent stage having the substrate effect is made lower than that of a MOS transistor in the preceding stage, thereby improving the reduction of the output voltage due to the substrate effect.
However, in this configuration as well, the increase of the threshold voltage Vt due to the substrate effect can not be suppressed. For example, in the case where the level of the power supply voltage Vdd is approximately halved (Vdd=1 to 1.5V), even if the number n of stages of the booster circuit is set to any value, the desired output voltage VPOUT can not be obtained. In addition, since the threshold voltages Vt of the MOS transistors are set to a plurality of different levels, for example, it is necessary to conduct the extra process of photomask and ion implantation. As a result, the manufacturing process becomes complicated. This is a disadvantage.
FIG. 22 shows a configuration of still another conventional semiconductor booster circuit.
As shown if FIG. 22, eight N-channel MOS transistors M1 to M8 are connected in series with one another to configure a booster circuit having four stages. Gate terminals of the transistors M1 to Mm8 are connected to respective drain terminals (represented by nodes N0 to N7). To the drain terminals N0, N2, N4 and N6, a clock signal xcfx86A as shown in FIG. 17 is input through capacitors C1, C3, C5 and C7, respectively. To the drain terminals N1, N3, N5 and N7, a clock signal xcfx86B which is in opposite phase with the clock signal xcfx86A is input through capacitors C2, C4, C6 and C8, respectively. In addition, substrate terminals of the transistors M1 to M8 are connected to a ground terminal (represented by a node N21). In addition, both a drain terminal and a gate terminal of each of the N-channel MOS transistors M20 and M21 are connected to an associated input terminal (represented by a node N20), and a substrate terminal thereof is connected to the ground terminal N21.
That is, the node N0 is respectively connected to the source terminal of the transistor M20, both the drain terminal and the gate terminal of the transistor M1, and one terminal of the capacitor C1. The node N1 is respectively connected to the source terminal of the transistor M21, both the drain terminal and the gate terminal of the transistor M2, the source terminal of the transistor M1 and one terminal of the capacitor C2. The node N2 is respectively connected to both the drain terminal and the gate terminal of the transistor M3, the source terminal of the transistor M2 and one terminal of the capacitor C3. The node N3 is respectively connected to both the drain terminal and the gate terminal of the transistor M4, the source terminal of the transistor M3 and one terminal of the capacitor C4. The node N4 is respectively connected to both the drain terminal and the gate terminal of the transistor M5, the source terminal of the transistor M4 and one terminal of the capacitor C5. The node N5 is respectively connected to both the drain terminal and the gate terminal of the transistor M6, the source terminal of the transistor M5 and one terminal of the capacitor C6. The node N6 is respectively connected to both the drain terminal and the gate terminal of the transistor M7, the source terminal of the transistor M6 and one terminal of the capacitor C7. In addition, the node N7 is respectively connected to both the drain terminal and the gate terminal of the transistor M8, the source terminal of the transistor M7 and one terminal of the capacitor C8. Further, an output terminal (represented by a node N8) of the semiconductor booster circuit is connected to the source terminal of the MOS transistor M8.
The above-mentioned expressions (1) and (2) are also applied to this booster circuit. Then, if the load current IOUT is zero, the capacitance ratio C/(C+Cs) is 1, and the amplitude voltage Vxcfx86 of the clock signal is equal to the power supply voltage Vdd in the expression (1), the voltage which is boosted per stage is expressed by (Vddxe2x88x92Vt).
Therefore, it is understood that the output voltage VPOUT is influenced by the margin between the threshold voltage Vt of each of the MOS transistors and the power supply voltage Vdd. In particular, it is understood that when the relation of Vtxe2x89xa7Vdd is established, the boosting operation is not performed in the corresponding stage. That is, if the threshold voltage Vt is increased, the voltage which is boosted per stage becomes either small or zero. Therefore, even if the number n of stages of the booster circuit is increased, the output voltage VPOUT is hardly or never increased. For example, since the source potential of the MOS transistor shown in FIG. 22 is equal to the output voltage VPOUT, and the substrate potential is 0V, the substrate bias voltage Vbs is equal to the output voltage VPOUT. Now, since the booster circuit shown in FIG. 22 is provided for generating the positive high voltage, the output voltage VPOUT takes one of positive values. Therefore, the threshold voltage of the MOS transistor M8 becomes very high, and hence the boosting efficiency is reduced. This problem becomes especially pronounced during the low power source voltage operation in which the margin between the threshold voltage Vt and the power supply voltage Vdd is small.
In this booster circuit, as shown in FIG. 22, all the substrate terminals of the MOS transistors M1 to M8 are grounded. That is, the MOS transistors M1 to M8 are, as shown in FIG. 23, respectively constituted by sources/drains 454 to 462, which are formed in a P type semiconductor substrate 451, and gates 464 to 471, and the substrate terminal is connected to a ground terminal N21 through a P+ type impurity diffusion layer 452 in the semiconductor substrate 451. Incidentally, reference numeral 453 designates a drain of a MOS transistor 20 and reference numeral 463 designates a gate of the MOS transistor 20.
Therefore, there arises a problem that the potential of the source terminal of the MOS transistor, which is located in the more backward stage, becomes higher, and the difference in the potential between the source terminal and the substrate portion is increased so that due to the so-called substrate bias effect, the threshold voltage Vt is increased, and hence the output voltage VPOUT is limited due to the increase of the threshold voltage Vt.
It is therefore an object of the present invention to provide a semiconductor booster circuit in which a desired output voltage is capable of being obtained, even in the case where a level of a power supply voltage is low, without the necessity of the complicated manufacturing process.
A semiconductor booster circuit, according to the present invention, includes: a plurality of stages, each having a first MOS transistor and a first capacitor having one terminal connected to a drain terminal of the first MOS transistor, the stages being connected in series by connecting the first MOS transistors of the stages in cascade; and at least one of a first arrangement wherein a source terminal and a substrate of the first MOS transistor of each of the stages are electrically connected to each other and when the plurality of stages are divided into at least two groups, the substrates of the first MOS transistor included in each group are electrically insulated from the substrates of the first MOS transistors included in a different group and an arrangement wherein one terminal of a second capacitor is connected to a gate terminal of the first MOS transistor of each of the stages, and first clock signal generating means for inputting a first clock signal to the other terminal of the first capacitor, and second clock signal generating means for inputting a second clock signal having a larger amplitude than a power supply voltage to the other terminal of the second capacitor are provided.
The semiconductor booster circuit, according to a first aspect of the present invention, includes a plurality of stages, each having a first MOS transistor and a first capacitor having one terminal connected to a drain terminal of the MOS transistor, the stages being connected in series by connecting the MOS transistors of the stages in cascade wherein a source terminal and a substrate of the first MOS transistor of each of the stages are electrically connected to each other and when the plurality of stages are divided into at least two groups, the substrates of the first MOS transistors included in each group are electrically insulated from the substrates of the first MOS transistors included in a different group.
In one embodiment of the present invention, the first MOS transistor is a P-channel MOS transistor which is formed in an N type well region, and the N type well regions of the respective stages are electrically insulated from one another.
In one embodiment of the present invention, in each of the stages, a second capacitor having one terminal, which is connected to a gate terminal of the first MOS transistor, is provided, and also the gate terminal and the source terminal of the first MOS transistor are connected to each other through a second MOS transistor, and a gate terminal of the second MOS transistor is connected to the one terminal of the first capacitor.
In one embodiment of the present invention, a pair of first clock signals which are in opposite phase with each other are respectively inputted to the two other terminals of the first capacitors in the two continuous stages, and a pair of second clock signals which are different in pulse timing from each other are respectively inputted to the two other terminals of the second capacitors in the two continuous stages.
In one embodiment of the present invention, in each of the stages, the gate terminal of the first MOS transistor in the preceding stage is connected to the one terminal of the first capacitor in the subsequent stage, and a pair of clock signals which are in opposite phase with each other are respectively inputted to the two other terminals of the first capacitors in the two continuous stages.
In one embodiment of the present invention, each of the stages includes a first MOS transistor and a first capacitor having one terminal connected to a source terminal of the first MOS transistor, wherein the stages are connected in series by connecting the first MOS transistors of the respective stages in cascade, a gate terminal and the source terminal of the first MOS transistor in each stage are electrically connected to each other, and also the source terminal and the substrate thereof are electrically connected to each other and the substrate is electrically insulated from the substrate of the first MOS transistors in another stage.
Incidentally, in a preferred aspect of the present invention, the first MOS transistor is an N-channel MOS transistor which is formed in a P type well region, and the P type well regions of the respective stages are electrically insulated from one another.
In the first aspect of the present invention, the substrate of the MOS transistor forming each of the stages of the booster circuit is electrically insulated from the substrate of the MOS transistor of another stage, and in each of the stages, the substrate and the source terminal of the MOS transistor are electrically connected to each other, whereby the potential at the substrate of the MOS transistor is fixed to the source potential. Hence the increase of the threshold voltage of the MOS transistor due to the substrate effect is effectively suppressed.
A semiconductor booster circuit, according to a second aspect of the present invention, includes: a plurality of stages, each having a first MOS transistor, a first capacitor having one terminal connected to a drain terminal of the first MOS transistor, and a second capacitor having one terminal connected to a gate terminal of the first MOS transistor, the stages being connected in series by connecting the first MOS transistors in the respective stages in cascade; first clock signal generating means for inputting a first clock signal to the other terminal of the first capacitor and second clock signal generating means for inputting a second clock signal having a larger amplitude than a power supply voltage to the other terminal of the second capacitor.
In one embodiment of the present invention, the first clock signal includes a pair or clock signals which are in opposite phase with each other, and the pair of clock signals are respectively inputted to the two first capacitors in the two consecutive stages.
In one embodiment of the present invention, in each of the stages, the gate terminal and the drain terminal of the first MOS transistor are connected to each other through a second MOS transistor, and a gate terminal of the second MOS transistor is connected to the other terminal of the first capacitor in the subsequent stage.
In the second aspect of the present invention, in order to drive the MOS transistors to perform the boosting operation, other clock signals are employed which are different from the clock signals which are used to drive the stages and have a larger amplitude than the power supply voltage, whereby it is possible to secure the threshold for conducting the MOS transistor and also it is possible to prevent the reduction of the output voltage due to the substrate effect.
A semiconductor booster circuit, according to a third aspect of the present invention, includes: a plurality of stages, each having a first MOS transistor and a first capacitor having one terminal connected to a drain terminal of the first MOS transistor, the stages being connected in series by connecting the first MOS transistors of the respective stages in cascade, wherein a source terminal and a substrate of the first MOS transistor in each of the stages are electrically connected to each other, and when the plurality of stages are divided into at least two stages, the substrates of the first MOS transistors included in each group are electrically insulated from the substrates of the first MOS transistors included in another group; and wherein one terminal of a second capacitor is connected to a gate terminal of the first MOS transistor in each of the stages, and first clock signal generating means for inputting a first clock signal to the other terminal of the first capacitor in each stage, and second clock signal generating means for inputting a second clock signal having a larger amplitude than a power supply voltage to the other terminal of the second capacitor in each stage are provided.
In one embodiment of the present invention, the first MOS transistor is a P-channel MOS transistor which is formed in an N type well region, and the N type well regions in the respective stages are electrically insulated from one another.
In one embodiment of the present invention, in each of the stages, the gate terminal and the source terminal of the first MOS transistor are electrically connected to each other through a second MOS transistor, and a gate terminal of the second MOS transistor is connected to the one terminal of the first capacitor.
In one embodiment of the present invention, the first clock signal includes a pair of clock signals which are in opposite phase with each other, and the pair of clock signals are respectively inputted to the first capacitors in the two consecutive stages.
In the third aspect of the present invention, the substrate of the MOS transistor constituting each of the stages of the booster circuit is electrically insulated from the substrate of the MOS transistor in another stage, and also in each of the stages, the substrate and the source terminal of the MOS transistor are electrically connected to each other, whereby the potential at the substrate of the MOS transistor is fixed to the source potential. Hence the increase of the threshold voltage of the MOS transistor due to the substrate effect is suppressed.
In addition, the gate voltage of the MOS transistor which operates to perform the boosting operation in the stages is controlled by the clock signals other an the source voltage and the drain voltage, and the amplitude of each of the clock signals is made larger than the input power supply voltage of the booster circuit, whereby since even in the employment of the low power supply voltage, the MOS transistor can be sufficiently rendered to an on state, and also the voltage drop due to the threshold voltage of the MOS transistor is eliminated so that the boosting capability is improved.
A semiconductor booster circuit, according to a fourth aspect of the present invention, includes a plurality of stages, each of the stages having two first MOS transistors which are connected in series with each other and two capacitors, each having one terminal connected to a drain or source terminal of one of the first MOS transistors, the series circuits of the first MOS transistors of the respective stages being connected in series between an input side and an output side, wherein the plurality of stages are divided into at least two groups, and substrates of the first MOS transistors included in the stages of each group are formed integrally in a conductive substrate portion, and the potentials which are applied to the substrate portions of the groups are controlled independently of one another.
In one embodiment of the present invention, the booster circuit operates for generating a positive high voltage and the substrate portions of the first MOS transistors included in the more backward stage are controlled at a higher potential.
In one embodiment of the present invention, the first MOS transistor is a P-channel MOS transistor which is formed in an N type well region, and the N type well regions of the respective groups are electrically insulated from one another.
In one embodiment of the present invention, the booster circuit operates for generating a negative high voltage and the substrate portions of the first MOS transistors included in the more backward stage are controlled at a negative lower potential.
In one embodiment of the present invention, the first MOS transistor is an N-channel MOS transistor which is formed in a P type well region, and the P type well regions of the respective groups are electrically insulated from one another.
In one embodiment of the present invention, the substrate of the first MOS transistor of each stage is connected to a drain terminal or a source terminal of the first MOS transistor which is located at the preceding stage of the group to which the first MOS transistor belongs.
In one embodiment of the present invention, second capacitors each having one terminal connected to the gate terminal of one of the first MOS transistors are provided, and the gate terminal and the source or drain terminal of each of the first MOS transistors are connected to each other through a second MOS transistor, and the gate terminal of the second MOS transistor is connected to the one terminal of the first capacitor.
In one embodiment of the present invention, in each of the stages, the substrate of the second MOS transistor is connected to the substrate of the first MOS transistor.
In one embodiment of the present invention, a pair of first clock signals which are in opposite phase with each other are respectively inputted to the other terminals of the two adjacent first capacitors, and also a pair of second clock signals which are different in pulse timing from each other are respectively inputted to the other terminals of the two adjacent second capacitors.
In the fourth aspect of the present invention, since the substrate portions of the MOS transistors constituting the booster circuit are divided into groups and the potentials of the substrate portions in the respective groups are controlled independently of one another, the potentials at the substrate portions of the MOS transistors of each group can be fixed to a potential different from that of another group. Therefore, it is possible to suppress the increase of the threshold voltage of the MOS transistor due to the substrate bias effect, and also the level of the output voltage can be made higher than that in the conventional booster circuit.